1. Field of the Invention
This invention relates to a semiconductor device fabrication method involving the step of lift-off patterning of a metal film for forming electrodes and wiring.
2. Description of the Related Art
As a patterning method for electrodes and wiring of semiconductor devices, lift-off processing is used in many cases, in which, as illustrated in FIG. 1A, a resist layer 43 is formed on a semiconductor wafer 41 as a mask, followed by vacuum deposition of a metal film 45 on the resist layer 43, and subsequent immersion thereof in an organic solvent such as acetone or the like to remove the resist layer 43 and the metal film 45 formed thereon.
In this lift-off patterning, a thin sidewall deposition layer 45s is formed on a sidewall of the resist layer 43 by scattered metal particles being deposited thereon during the vacuum deposition of the metal film 45. This sidewall deposition layer 45s prevents the organic solvent from permeating the resist layer 43. For this reason, there is typically used a method for breaking the sidewall deposition layer 45s by applying physical force such as ultrasonic oscillation or the like while immersing the semiconductor wafer 41 in the organic solvent.
Because the cross-section of the positive type resist layer 43 typically used is in a not vertical but slightly forward tapered shape, however, making the metal film 45 thick also makes the sidewall deposition layer 45s thick, which causes difficulty in lift-off, and consequently makes the length of time for the processing long.
Further, as illustrated in FIG. 1B, portion of the sidewall deposition layer 45s which is not completely removed by lift-off is deposited as a burr 45a on the specified-pattern metal film 45 formed subsequent to lift-off processing, or as a burr 45h on the wafer surface adjacent to the metal film 45, or left as a burr 45c in such a manner as to protrude from the metal film 45. As a consequence, there is the problem that a wiring short-circuiting or multilayer wiring disconnection or short-circuiting takes place. For that reason, to make the sidewall deposition layer 45s of the resist layer 43 thin, various attempts have been made to the cross-sectional shape of the resist layer 43.
For example, its methods are exemplified by: as illustrated in FIG. 2A, forming the cross-section of a resist layer 51 in a substantially T-shape (the surface layer of the resist layer 51 in a visor shape), by exposing the positive type resist layer 51 to light, followed by chlorobenzene treatment or deep UV light irradiation to make the surface layer of the resist layer 51 insoluble to a developer, and subsequent development; or as illustrated in FIG. 2B, forming the cross-section of a resist layer 61 in an inverse tapered shape, by forming one resist layer 61, followed by light exposure of its entire surface to form a further resist layer 61 thereon, patterned light exposure and development.
In these methods, however, there is the problem of a drop in precision for resist patterning. As illustrated in FIG. 2C, on the other hand, there is the method for forming the cross-section of a resist layer 71 in a vertical or inverse tapered shape, by image inversion of a positive type resist layer into a negative type resist layer, and subsequent development, which however also poses the problems with the vertical pattern having little effect on making the sidewall deposition layer 45s thin, or with the inverse tapered shape having to intentionally reduce resolution for resist patterning, and making the shape uncontrollable.
As a solution to such problems, there is a fabrication method for a semiconductor device, in which on a substrate or a coating film formed thereover, there is formed a photoresist film consisting of a surface resist layer inverted by only heat treatment after light exposure, and an underlying resist layer formed of a diazo novolac photoresist (see e.g., Japanese patent No. 3339331).
According to the semiconductor device fabrication method described in Japanese patent No. 3339331, since during vacuum deposition of a conductive film, metal particles incident diagonally from a resist pattern are blocked by the surface resist layer formed in a forward tapered shape, no deposition metal particles are deposited on the underlying resist layer processed in an undercut shape As a result, there is formed no sidewall deposition layer joined to a metal pattern that serves as electrodes and wiring, which allows the length of time for lift-off processing to be greatly reduced, while preventing burrs from being produced around the metal pattern formed by lift-off processing.
Because the semiconductor device fabrication method described in Japanese patent No. 3339331 forms the surface resist layer in a forward tapered shape, however, there is a limit on adaptation to a micro metal pattern that serves as electrodes and wiring of the semiconductor device, and it is difficult to ensure precision for micro metal pattern shape, which is because, generally, in forward tapered shapes, precision for tapered shapes has a larger effect on the precision for metal pattern shape subsequently formed than in inverse tapered shapes. In other words, in inverse tapered shapes, since the outermost-protruding portion is positioned at its top, even in case of some minor errors in taper angle, its effect on the precision for metal pattern shape subsequently formed is small, whereas, in forward tapered shapes, since the outermost-protruding portion is positioned at its bottom, even in case or small errors in taper angle, its effect on the precision for metal pattern shape subsequently formed is large.